SOC Clocks RTL Design Engineer

The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The NVIDIA System-On-Chip (SOC) group is looking for a strong RTL Design Engineer to own the SOC clocking logic for our next-generation networking chips. Clocks are the backbone of the SOC. In this role you will own the clock generation, distribution, and control logic for the entire chip — PLL and reference clock integration, clock muxing and dividers, glitchless switching, clock gating, reset synchronization, and the clock domain crossing infrastructure that every unit on the die depends on.This is an RTL design role, not a circuit or transistor-level design role. You will translate micro-architecture specifications into high-quality synthesizable RTL, and drive that RTL through to silicon in close partnership with the micro-architecture, Design Verification, and Physical Design (backend) teams. You will also interact with CAD, Package Design, Software, and DFT teams.What you'll be doing:Owning the SOC clocking logic end to end: writing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing, division, glitchless switching, gating, and reset synchronization, from micro-architecture specification through tape-outDefining and implementing the SOC clock and reset architecture together with the micro-architecture team — collecting clocking requirements from every unit on the chip and turning them into a coherent, verifiable designOwning clock domain crossing infrastructure and CDC closure across the SOCPartnering with the micro-architecture team to review specifications, close on design intent, and provide feedback on implementation cost, timing, area, and powerWorking hand-in-hand with the Physical Design (backend) team on clock tree implementation and constraints, partitioning, floorplan and timing feedback, trial synthesis, congestion and timing convergence, and physical design readinessSupporting Software and firmware teams on clock programming sequences, DVFS, and low-power/clock-shutdown flowsDriving design quality: lint, CDC/RDC, formal checks, synthesis QoR, connectivity and structural checksSupporting SOC-level chip build and assembly, and developing/deploying automation flows that make RTL integration and design quality checking repeatable and scalableSupporting emulation, firmware, and post-silicon bring-up customers of your designWhat we need to see:B.Sc./M.Sc. in Electrical Engineering or Computer Engineering3+ years of relevant experience in RTL/logic designSolid hands-on RTL design skills in Verilog/SystemVerilog, with a good understanding of synthesis, timing, and how RTL choices affect the physical implementationExperience taking a design from micro-architecture specification through verification and physical implementationSolid understanding of clocking and reset concepts: clock gating, clock muxing and dividers, glitchless clock switching, reset synchronization, and clock domain crossingFamiliarity with design quality tooling (lint, CDC/RDC, formal, synthesis)Great teammate with strong communication skills across micro-architecture, DV, and backend teamsWays to stand out from the crowd:Passion for quality, and a track record of clean deliveries to physical design, DV, emulation, firmware, and other downstream customersPrior ownership of SOC-level clocking or reset architecture on a taped-out chipExperience with PLL/clock generator integration and clock tree constraint development with backend teamsAt NVIDIA, you will be immersed in a diverse and encouraging environment where everyone is encouraged to do their best work. Join us and see how you can make a lasting impact on the world.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law